The shift register length is determined by clocking in ones to form a walking one (or zero) pattern. The length of zeroes (or 1s) used is a large number representing the longest shift register that could be implemented. The microcontroller ( 82) fills the digital input shift registers with zeros (or 1s) by clocking in a long string of zeros (or 1s) using the data output bus 112 and clock 114. For the digital inputs (in module 300), the microcontroller ( 82) changes the CHANNEL SELECT signal 12 to select the digital input channel of the multiplexer 70 so that the output of the right most digital input shift register (shown as 74A) is connected to the data input bus 234. Finally, a walking one (1) (or zero (0)) is shifted through to determine the length of the shift registers. Next, zeroes (or ones (1s)) are shifted through the shift registers and/or converters associated with the selected channel. First a multiplexer channel associated with the I/O type is selected using the channel select signal 12. H03M9/00- Parallel/series conversion or vice versaĪs part of system 10 initialization, the number of input/output (“I/O”) bits is determined. #Analog parallel to serial converter code#H03M- CODING DECODING CODE CONVERSION IN GENERAL.238000005516 engineering process Methods 0.000 description 1.238000006243 chemical reaction Methods 0.000 description 2.238000004891 communication Methods 0.000 claims description 13.Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.) Filing date Publication date Priority to US11/196,691 priority Critical patent/US7180437B1/en Application filed by Boeing Co filed Critical Boeing Co Priority to US11/566,101 priority patent/US7312735B2/en Publication of US20070093915A1 publication Critical patent/US20070093915A1/en Application granted granted Critical Publication of US7312735B2 publication Critical patent/US7312735B2/en Links Original Assignee Boeing Co Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.) Le Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.) Active Application number US11/566,101 Other versions US20070093915A1 #Analog parallel to serial converter pdf#Google Patents Parallel-to-serial converterĭownload PDF Info Publication number US7312735B2 US7312735B2 US11/566,101 US56610106A US7312735B2 US 7312735 B2 US7312735 B2 US 7312735B2 US 56610106 A US56610106 A US 56610106A US 7312735 B2 US7312735 B2 US 7312735B2 Authority US United States Prior art keywords digital inputs analog data module Prior art date Legal status (The legal status is an assumption and is not a legal conclusion. Google Patents US7312735B2 - Parallel-to-serial converter US7312735B2 - Parallel-to-serial converter
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